Electronic device, in particular for protection against overvoltages

ABSTRACT

An electronic device is formed by a sequence of at least two thyristors coupled in series in a same conduction direction. Each thyristor has a gate of a first conductivity type. The gates of the first conductivity type for the thyristors in the sequence are coupled together in order to form a single control gate.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a divisional of U.S. application for patent Ser. No.15/096,975 filed Apr. 12, 2016, which claims priority from FrenchApplication for Patent No. 1561135 filed Nov. 19, 2015, the disclosuresof which are incorporated by reference.

TECHNICAL FIELD

Embodiments of the invention relate to electronic devices, such aselectronic devices based on thyristors, also referred to by a personskilled in the art by the acronym “SCR” (“Silicon ControlledRectifier”), and especially those designed to protect components againstovervoltages, in particular overvoltages such as parasitic overvoltagesproduced during operation of the component, but also overvoltagesoccurring during electrostatic discharges (“ElectroStatic Discharge”:ESD).

BACKGROUND

Conventionally, a thyristor is made to conduct when the voltage acrossits terminals becomes greater than a trigger voltage.

Further to the trigger voltage, another important parameter of athyristor is the holding voltage, that is to say the minimum voltagesuch that the thyristor remains conductive after having been triggered.

In certain applications, thyristors have a high trigger voltage, forexample around 3.6 V, but a low holding voltage, for example around 1.2V, which may then be less than the rated supply voltage of theintegrated circuit incorporating such thyristors. This is the case, forexample, with an integrated circuit having a supply voltage of 3.3 V.

Consequently, during operation of the integrated circuit, the thyristorsmay be triggered and become conductive during an electrical overstress(“Electrical OverStress”: EOS) and then continue to conduct until theyare destroyed, because the supply voltage of the circuit is then alwaysgreater than the holding voltage of these thyristors.

One solution, based on a protective device having a structure of threecascoded thyristors, is generally proposed in order to increase theholding voltage of such a protective device.

However, such a structure with three thyristors also increases thetrigger voltage and the surface occupancy of the device on silicon.

SUMMARY

Thus, according to one embodiment, it is proposed to improve theperformance of protective electronic devices based on thyristors byincreasing the holding voltage without significantly increasing thetrigger voltage.

According to another embodiment, it is proposed to produce such a devicewithout having a significant effect on the surface occupancy on silicon.

One aspect proposes an electronic device comprising a sequence of atleast two thyristors coupled in series in the same conduction direction(the anode and the cathode of two adjacent thyristors of the sequenceare connected), each thyristor having a gate of a first conductivitytype, all the gates of the first conductivity type of the thyristorsbeing coupled in order to form a single gate.

Thus, the thyristors of the sequence are so to speak “merged” byconnecting their gates of the same conductivity type in order to form adevice having a single gate, for example of the first conductivity type,which will be connectable to a single trigger circuit. The holdingvoltage of the device is thus increased without significantlyincreasing, or even without modifying, the trigger voltage in comparisonwith that of a single thyristor, this trigger voltage being moreovermuch less than that of the cascoded structure of the prior art.

By way of indication but without limitation, the gates areadvantageously of N-type conductivity, although they could be of P-typeconductivity.

According to one embodiment, all the thyristors of the electronic deviceare arranged in the same semiconductor body having the firstconductivity type.

Each thyristor has, within the semiconductor body, a first semiconductorregion having a second conductivity type opposite to the firstconductivity type and a second semiconductor region having the secondconductivity type and including a semiconductor zone having the firstconductivity type.

The first semiconductor region of a thyristor of the sequence is coupledby a metallization lying above the semiconductor body to thesemiconductor zone of the preceding thyristor in the sequence. Thesemiconductor body forms the single gate.

Such an embodiment makes it possible to limit the surface occupancy onsilicon.

Furthermore, the semiconductor body has, for example, a zone doped moreheavily than the rest of the body. This may surround all thesemiconductor regions and form a contact for the single gate.

The electronic device furthermore advantageously has a trigger circuitcoupled to the single gate.

According to a preferred embodiment, the sequence of thyristorscomprises a first thyristor and a second thyristor. The anode of thesecond thyristor is coupled to the cathode of the first thyristor.

According to this preferred embodiment, the trigger circuit is coupledto the single gate and to the cathode of the second thyristor.

Such a structure with two thyristors coupled in series mayadvantageously reduce by up to 40% the surface occupancy compared withthe solution with three cascoded thyristors, while offering a higherholding voltage and a threshold voltage substantially equal to that ofan electronic device having a single thyristor.

The electronic device may be used to protect a component arrangedbetween the two ends of the sequence of thyristors. The trigger circuitmay, for example, be coupled to the single gate and to one of the endsof the sequence.

In an embodiment, an integrated circuit comprises: a semiconductor bodyhaving a first conductivity type; a first semiconductor region in thesemiconductor body having a second conductivity type opposite to thefirst conductivity type; a second semiconductor region in thesemiconductor body having the second conductivity type; wherein thefirst semiconductor region is separated from the second semiconductorregions by a first portion of the semiconductor body; and a firstheavily doped region of the first conductivity type formed as a ringsurrounding the first and second semiconductor regions and furtherextending through said first portion of the semiconductor body betweenthe first and second semiconductor regions.

BRIEF DESCRIPTION OF THE DRAWINGS

Other advantages and characteristics of the invention will becomeapparent on studying the detailed description of embodiments which aretaken by way of non-limiting examples and illustrated by the appendeddrawings, in which:

FIG. 1 is a schematic diagram of an electronic device;

FIG. 2 is a top view of an integrated circuit fabrication of the deviceof FIG. 1;

FIG. 3 is a cross sectional view of the integrated circuit fabrication;and

FIG. 4 is a further schematic diagram of an electronic device.

DETAILED DESCRIPTION

FIG. 1 schematically illustrates an example of an electronic device DE.

The device DE illustrated in FIG. 1 comprises a first thyristor TH1 anda second thyristor TH2, which are connected in series in the sameconduction direction between a first terminal B1 and a second terminalB2. In this context, the phrase “in the same conduction direction” isintended to mean a connection between the anode and the cathode of twoadjacent thyristors of the sequence.

The thyristor TH1 has an anode A1 coupled to the first terminal B1, acathode K1 and a gate G1, for example the N-type gate. The thyristor TH2has an anode A2 coupled to the cathode K1, a cathode K2 coupled to thesecond terminal B2, and its N-type gate G2 coupled to the gate G1 so asto form a single N-type gate GU.

Reference will now be made to FIG. 2, which shows a diagram of theimplementation of the electronic device DE described above andillustrated in FIG. 1 on silicon, and to FIG. 3, which is a view insection along the line of FIG. 2.

The thyristors TH1 and TH2 are formed in the same semiconductor body CS,for example of the N type.

Each thyristor TH1 or TH2 has, in the body CS, a first semiconductorregion RS1 of P-type conductivity having a first semiconductor zoneZSFD1 doped more heavily (of the P+ type). This first region RS1 formsthe anode A1 or A2 of the thyristor TH1 or TH2, and the firstsemiconductor zone ZSFD1 forms a contacting region of the anode A1 orA2. The anode A1 of the first thyristor TH1 is connected to the firstterminal B1 of the electronic device DE.

Each thyristor TH1 or TH2 furthermore has, in the body, a secondsemiconductor region RS2 of the P type containing a second semiconductorzone ZSFD2 of the opposite conductivity type and doped more heavily (N+type). The second semiconductor zones ZSFD2 respectively form thecathodes K1 and K2 of the thyristors TH1 and TH2.

The second semiconductor region RS2 of each thyristor forms the P-typegate of this thyristor and furthermore has a third semiconductor zoneZSFD3 of the same conductivity type and doped more heavily (P+ type).The P-type gate is in this case short-circuited with the cathode zoneZSFD2 by a metallization (not represented in the figures) between thezones ZSFD2 and ZSFD3, because it is not used as a trigger gate.

The anode A2 of the second thyristor TH2 is connected to the cathode K1of the first thyristor TH1 by a metallization lying above the body CS,and the cathode of the second thyristor is connected to the secondterminal B2.

The entire semiconductor body CS forms de facto the single N-type gateGU of the electronic device DE.

In this regard, the semiconductor body CS advantageously has a contactzone ZCFD doped more heavily than the rest of the body CS. This contactzone ZCFD surrounds all the semiconductor regions RS1 and RS2 and formsa contacting zone of the single N-type gate GU.

Such an integrated electronic device DE having two thyristors TH1 andTH2 advantageously makes it possible to reduce by up to 40% the surfaceoccupancy compared with the solution of a protective device having astructure with three cascoded thyristors.

As regards the trigger voltage and the holding voltage of such a device,they are respectively of the order of 3.6 volts and 4 volts forimplementation in a 28 nm CMOS technology.

Such a device is therefore highly suitable for protecting a component ofan integrated circuit supplied with a supply voltage of 3.3 voltsagainst overvoltages occurring during operation of the component.

Reference will now be made in this regard more particularly to FIG. 4 inorder to illustrate an example of the application of the electronicdevice DE for the protection of a component 1 coupled between the firstterminal B1 and the second terminal B2. For example, the component 1 maybe a microcontroller or a processor core.

The first terminal B1 may, for example, be an input/output terminal(“I/O pad”) of the integrated circuit containing the component, and theterminal B2 may be intended to be grounded.

As illustrated in FIG. 4, the device DE has a trigger circuit connectedin this case between the single gate GU and the terminal B2.

The trigger circuit CD may be based on MOS transistors with hybridoperation, as described in the international patent application WO2011/089179 or U.S. Pat. No. 9,019,666 (incorporated by reference).Specifically, it has been shown in this international patent applicationWO 2011/089179 that such transistors may also be used to form a triggercircuit.

More precisely, the trigger circuit CD in this case has a first NMOStransistor TN1 with hybrid operation, the gate GN1 and the substrateSBN1 of which are connected together to the source SN1 of the transistorTN1 by a first resistor R1, and a second NMOS transistor TN2 with hybridoperation, the drain DN2 of which is connected to the source SN1 of thefirst transistor TN1, and the gate GN2 and substrate SBN2 of which areconnected together to the source SN2 of the second transistor TN2 by asecond resistor R2, the source SN2 of this second transistor TN2 beingconnected to the cathode K2 of the second thyristor TH2 and therefore tothe second terminal B2.

Other conventional structures of trigger circuits (not illustrated), forexample MOS transistors whose gate and substrate are connected to earth(here to the terminal B2), which are commonly referred to by a personskilled in the art by the acronym “GGNMOS” (“Grounded-Gate NMOS”), arealso possible.

It should be noted that the trigger circuit CD may advantageously be atrigger circuit identical to that implemented in a conventionalprotective device having a single thyristor.

Thus, with a trigger voltage of the order of 3.6 volts, a holdingvoltage of the order of 4 volts and a supply voltage of 3.3 volts,triggering in the event of an overstress on the component duringoperation does not maintain a conductive state of the electronic deviceDE at the end of the overstress.

Thus, an electronic device for protection against overvoltages isobtained which has a high holding voltage while avoiding a significantincrease in the trigger voltage compared with a protective device havinga single thyristor. Such an electronic device advantageously requires areduced surface occupancy on silicon compared with a protective devicehaving three thyristors.

Of course, such a device may also be used to protect the componentagainst electrostatic discharges (ESD) when the component is not inoperation, i.e. not supplied.

It would be possible to increase further the number of thyristors of thesequence, their gates being connected together in order to form thesingle gate. This would make it possible to increase the holding voltageof the overall device further. In this case, the number of elements ofthe trigger circuit, for example the number of transistors with hybridoperation connected in series, would be increased accordingly incomparison with the embodiment of FIG. 4.

From an integration point of view, all the thyristors would then beproduced in the same semiconductor body CS (FIGS. 2 and 3), with theanode of one thyristor of the sequence connected by a metallization tothe cathode of the thyristor preceding it in the sequence.

1. An integrated circuit, comprising: a semiconductor body having afirst conductivity type; and a first thyristor formed in saidsemiconductor body, comprising: a first semiconductor region in thesemiconductor body having a second conductivity type opposite to thefirst conductivity type, the first semiconductor region forming an anodeof the first thyristor; a second semiconductor region in thesemiconductor body having the second conductivity type, the first andsecond semiconductor regions separated from each other by a portion ofthe semiconductor body, the second semiconductor region forming acathode of the first thyristor; and wherein the semiconductor body formsa cathode control gate of the first thyristor.
 2. The integrated circuitof claim 1, further comprising a first heavily doped region of the firstconductivity type formed in said portion of the semiconductor body andconfigured to provide a contact for said cathode control gate.
 3. Theintegrated circuit of claim 2, wherein said first heavily doped regionof the first conductivity type surrounds the first and secondsemiconductor regions and passes between the first and secondsemiconductor regions.
 4. The integrated circuit of claim 2, furthercomprising: a second heavily doped region of the second conductivitytype formed within the first semiconductor region; and a third heavilydoped region of the first conductivity type formed within the secondsemiconductor region.
 5. The integrated circuit of claim 4, furthercomprising a fourth heavily doped region of the second conductivity typeformed within the second semiconductor region and in contact with thethird heavily doped region.
 6. The integrated circuit of claim 5,wherein the fourth heavily doped region is shorted to the third heavilydoped region.
 7. The integrated circuit of claim 1, further comprising asecond thyristor formed in said semiconductor body, comprising: a thirdsemiconductor region in the semiconductor body having the secondconductivity type, the third semiconductor region forming an anode ofthe second thyristor; a fourth semiconductor region in the semiconductorbody having the second conductivity type, the third and fourthsemiconductor regions separated from each other by the portion of thesemiconductor body, the fourth semiconductor region forming a cathode ofthe second thyristor; and wherein the semiconductor body forms a cathodecontrol gate of both the first and second thyristors.
 8. The integratedcircuit of claim 7, further comprising an electrical connectionconfigured to connect the cathode of the first thyristor to the anode ofthe second thyristor.
 9. The integrated circuit of claim 7, furthercomprising: a first heavily doped region of the first conductivity typeformed in said portion of the semiconductor body separating the firstand second semiconductor regions and configured to provide a contact forsaid cathode control gate of the first thyristor; and a second heavilydoped region of the first conductivity type formed in said portion ofthe semiconductor body separating the third and fourth semiconductorregions and configured to provide a contact for said cathode controlgate of the second thyristor.
 10. The integrated circuit of claim 9,further comprising: a third heavily doped region of the firstconductivity type formed in a portion of the semiconductor bodyseparating the first and second thiyristors and configured to provide acontact for said cathode control gate of the first and secondthyristors.
 11. An integrated circuit, comprising: a semiconductor bodyhaving a first conductivity type; a first semiconductor region in thesemiconductor body having a second conductivity type opposite to thefirst conductivity type; a second semiconductor region in thesemiconductor body having the second conductivity type; wherein thefirst semiconductor region is separated from the second semiconductorregions by a first portion of the semiconductor body; and a firstheavily doped region of the first conductivity type formed as a ringsurrounding the first and second semiconductor regions and furtherextending through said first portion of the semiconductor body betweenthe first and second semiconductor regions.
 12. The integrated circuitof claim 11, further comprising: a second heavily doped region of thesecond conductivity type formed within the first semiconductor region;and a third heavily doped region of the first conductivity type formedwithin the second semiconductor region.
 13. The integrated circuit ofclaim 12, further comprising a fourth heavily doped region of the secondconductivity type formed within the second semiconductor region and incontact with the third heavily doped region.
 14. The integrated circuitof claim 13, wherein the fourth heavily doped region is shorted to thethird heavily doped region.
 15. The integrated circuit of claim 12,wherein the second heavily doped region is an anode terminal of athyristor, the third heavily doped region is a cathode terminal of thethyristor and the first heavily doped region is a control gate of thethyristor.